The present invention generally relates to processing a semiconductor substrate. In particular, the present invention relates to a polymer memory device and a method of manufacturing the polymer memory device.
The volume, use and complexity of computers and other electronic devices are persistently increasing. As computers continually become more powerful, new and improved electronic devices are continuously developed (e.g., digital audio players, video players). Additionally, the growth and use of digital media (e.g., digital audio, video, images, and the like) have further pushed development of these devices. This growth and development has vastly increased the amount of information desired/required to be stored and maintained for computer and electronic devices.
Memory devices generally include arrays of memory cells. Each memory cell can be accessed or xe2x80x9creadxe2x80x9d, xe2x80x9cwrittenxe2x80x9d, and xe2x80x9cerasedxe2x80x9d with information. The memory cells maintain information in an xe2x80x9coffxe2x80x9d or an xe2x80x9conxe2x80x9d state (e.g., are limited to 2 states), also referred to as xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d. Typically, a memory device is addressed to retrieve a specified number of byte(s) (e.g., 8 memory cells per byte). For volatile memory devices, the memory cells must be periodically xe2x80x9crefreshedxe2x80x9d in order to maintain their state. Such memory devices are usually fabricated from semiconductor devices that perform these various functions and are capable of switching and maintaining the two states. The devices are often fabricated with inorganic solid state technology, such as, crystalline silicon devices. A common semiconductor device employed in memory devices is the metal oxide semiconductor field effect transistor (MOSFET).
Because of the increasing demand for information storage, memory device developers and manufacturers are constantly attempting to increase storage capacity for memory devices (e.g., increase storage per die or chip). A postage-stamp-sized piece of silicon may contain tens of millions of transistors, each transistor as small as a few hundred nanometers. However, silicon-based devices are approaching their fundamental physical size limits. Inorganic solid-state devices are generally encumbered with a complex architecture which leads to high cost and a loss of data storage density. The volatile semiconductor memories based on inorganic semiconductor material must constantly be supplied with electric current with a resulting heating and high electric power consumption in order to maintain stored information. Non-volatile semiconductor devices have a reduced data rate and relatively high power consumption and large degree of complexity.
Moreover, as the size of inorganic solid-state devices decreases and integration increases, sensitivity to alignment tolerances increases making fabrication markedly more difficult. Formation of features at small minimum sizes does not imply that the minimum size can be used for fabrication of working circuits. It is necessary to have alignment tolerances, which are much smaller than the small minimum size, for example, one quarter the minimum size.
Scaling inorganic solid-state devices raises issues with dopant diffusion lengths. As dimensions are reduced, the dopant diffusion lengths in silicon are posing difficulties in process design. In this connection, many accommodations are made to reduce dopant mobility and to reduce time at high temperatures. However, it is not clear that such accommodations can be continued indefinitely. Furthermore, applying a voltage across a semiconductor junction (in the reverse-bias direction) creates a depletion region around the junction. The width of the depletion region depends on the doping levels of the semiconductor. If the depletion region spreads to contact another depletion region, punch-through or uncontrolled current flow, may occur.
Higher doping levels tend to minimize the separations required to prevent punch-through. However, if the voltage change per unit distance is large, further difficulties are created in that a large voltage change per unit distance implies that the magnitude of the electric field is large. An electron traversing such a sharp gradient may be accelerated to an energy level significantly higher than the minimum conduction band energy. Such an electron is known as a hot electron, and may be sufficiently energetic to pass through an insulator, leading to irreversibly degradation of a semiconductor device.
Scaling and integration makes isolation in a monolithic semiconductor substrate more challenging. In particular, lateral isolation of devices from each other is difficult in some situations. Another difficulty is leakage current scaling. Yet another difficulty is presented by the diffusion of carriers within the substrate; that is free carriers can diffuse over many tens of microns and neutralize a stored charge. Thus, further device shrinking and density increasing may be limited for inorganic memory devices. Furthermore, such device shrinkage for inorganic non-volatile memory devices while meeting increased performance demands is particularly difficult, especially while maintaining low costs.
The following is a summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not intended to identify key/critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention provides a method of manufacturing a polymer memory device which is formed within a via. More specifically, copper contacts and/orbit lines are formed within a metal-containing layer. One or more via openings can then be formed in an overlying dielectric layer to expose one or more of the copper contacts and/or bit lines. A portion of the exposed copper is converted to copper sulfide (e.g., Cu2 S2 or Cu2S), which may act as a catalyst to facilitate selective polymer growth by way of chemical vapor deposition (CVD). The copper sulfide can also facilitate in the operation of the memory cell device since it is a conductive material. For example, the copper sulfide may operate as a passive layer employed to communicate and/or transmit information within and/or between one or more memory cells.
Alternatively and in accordance with an aspect of the present invention, a spin-on diluted polymer solution may be employed such that the solution is baked in order to fill at least a bottom portion of the via. In accordance with another aspect of the present invention, a solution of monomers may be applied and utilized to facilitate polymer growth in at least a bottom portion of the via.
Following formation of the polymer in a lower portion of the via, a top electrode material may be deposited over the memory structure in order to fill the remaining portion of the via. Excess and/or unwanted portions of the top electrode material can be removed by polishing such as by a chemical mechanical polish (CMP) process. Thereafter, the via includes a lower portion comprising a polymer material and an upper portion comprising a top electrode material.
One aspect of the present invention relates to a method of forming a polymer memory device. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon; forming at least one copper contact in the metal-containing layer; forming at least one dielectric layer over the copper contact; forming at least one via in the dielectric layer to expose at least a portion of the copper contact; forming a polymer material in a lower portion of the via; and forming a top electrode material layer in an upper portion of the via.
Another aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-oxide layer thereon; forming at least one of a copper bit line and a copper pad in the metal-oxide layer; forming at least one dielectric layer over the copper contact; forming at least one via in the dielectric layer to expose at least a portion of the at least one copper bit line and copper pad; growing a polymer material in a lower portion of the via; forming a top electrode material layer in an upper portion of the via; and forming a word line over at least the top electrode layer.
Yet another aspect of the present invention relates to a system of fabricating a polymer memory device in a via comprising: method of fabricating a polymer memory device in a via The system includes a means for providing a semiconductor substrate having at least one metal-containing layer thereon; a means for forming at least one copper contact in the metal-containing layer; a means for forming at least one dielectric layer over the copper contact; a means for forming at least one via in the dielectric layer to expose at least a portion of the copper contact; a means for forming a polymer material in a lower portion of the via; and a means for forming a top electrode material layer in an upper portion of the via.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.